1. Technical Field
The present disclosure relates to emulation of system-on-a-chip (SoC) devices for debugging, and, more specifically, to provide emulation capability for SoCs.
2. Description of the Related Art
A System-On-Chip (SoC) with embedded cores, such as DSP (Digital signal processing) core or ARM (Advanced RISC Machine) core, typically has the capability for emulation. Emulation is a process used in debugging hardware/software interactions or interfaces, as well as debugging software failures. The standard hardware used for this purpose is called emulators. A software tool chain (available from emulator vendor) analyzes the HDL (Hardware Description Language) design, synthesizes and optimizes the design. The emulation database thus created is used by a user to emulate his design and verify its functionality at a much faster pace than the conventional PC (personal computer) based simulators. The emulation hardware engines may have different architectures. Typically they may be FPGA (Field Programmable Gate array), LUT (Look-Up-Table) or high performance CPU (Central Processing Unit) array based structures.
At present, the role of emulation is growing rapidly in the integrated circuit design. Simulation of close to real chip scenarios and timely fixing of design bugs in the design cycle further drives the need for availability of an emulation platform at a very early stage in the design cycle. The mapping of a design on an emulator has many advantages. One advantage is design speedup. Yet, there are several issues while mapping the process of a mixed signal design on an SoC, especially with the analog components such as PLLs (Phase Locked Loops), DLLs (Delay Locked Loops), audio/video DACs (Digital-to-Analog Converters)/ADCs (Analog-to-Digital Converters). The analog components present on the SoC are not synthesizable in the normal emulation flow.
Considering memory architectures such as those that follow a DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) standard, reading a DDR SDRAM memory requires a finite delay on several signals such as clock, data strobes etc. The delay is provided on these signals by the DDR controller and pad logic architecture present on the chip. However, in case of SoCs, delay is inserted by an on chip delay element such as a DLL (Delay locked loop). The DLLs used for such analog applications are not synthesizable for emulation platforms.
Delays inserted by behavioral statements in HDL (Verilog/VHDL) for such analog components are also ignored by emulation synthesis tools. Synthesis tools for emulators may optimize multiple driven or undriven nets. Hence, care is taken while coding HDL as this may lead to deviation from expected behavior. Another possible technique may be the delay is inserted manually in the desired signal path for emulation. But this technique again is not suitable and decreases the efficiency of the emulation platforms.
In certain cases, a digital DLL is used. The digital DLL works on a digital locking technique and replaces analog DLLs but again, the emulation process is affected by other non-synthesizable components like digital phase detectors, etc. These implementations also require additional jitter control circuitries, which have no meaning for emulation systems.